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Allen et al. J Mater Inf 2024;4:35  https://dx.doi.org/10.20517/jmi.2024.72     Page 11 of 15

               increases. Generally, MAPbI  with larger crystal grain sizes corresponds to better PSC device performance
                                       3
               as larger crystal grains reduce the likelihood of recombination events and trap states at the grain boundary,
               resulting in improved charge carrier lifetime and mobility [39-42] .


               PSCs using optimally photonic cured MAPbI 3
               Next, we compare PSC performance for p-i-n type devices made using TA and PC MAPbI  films. NiO  is
                                                                                                       x
                                                                                             3
               chosen as the base HTL. All PC PSCs used the optimized PC condition PC 25. In addition to the annealing
               method, the MAPbI /NiO  interface is chemically modified. PSC J-V characteristics for all devices are
                                 3
                                      x
               shown in Figure 4 and Supplementary Table 5. The champion device J-V curves are shown in Figure 5.
               Using NiO  as the HTL, MAPbI  PSCs made by TA show PCEs of 10.3% ± 1.0%, while devices made by PC
                        x
                                          3
               25 show significantly worse J-V characteristics with an average PCE of 1.19% ± 0.75%. The PC PSCs
               primarily suffer in short-circuit current density (J ) with a still significant reduction to both open-circuit
                                                          sc
               voltage (V ) and fill factor, as seen in Figure 4 between black and red. These results are very unexpected as
                        oc
               the Fréchet distance calculated from the UV-vis absorption spectra taken on these devices [Supplementary
               Figure 6] is small, agreeing with the results of PC MAPbI  on ITO shown in Figure 1 and Table 1. Thus, the
                                                               3
               reduced J-V characteristics are not caused by the PC MAPbI  itself. Since our device structure is p-i-n,
                                                                     3
               MAPbI  is deposited on the HTL, which undergoes the same processing conditions as the MAPbI .
                     3
                                                                                                        3
               Consequently, there could be an unanticipated problem at the PC MAPbI /NiO  interface.
                                                                             3
                                                                                  x
               Previous work showed that MAPbI  and NiO  begin to react at temperatures as low as 120 °C with
                                                        x
                                               3
                                                                                            [23]
               significant damage occurring as temperatures approach 180 °C under steady state heating . The reaction
               causes the decomposition of MAPbI , severely degrading overall PSC J-V characteristics, consistent with
                                               3
               what we see in PSCs with PC MAPbI  on NiO  HTL . As displayed in Table 1, the peak interface
                                                                [22]
                                                          x
                                                  3
               temperature for condition PC 25 simulated by SimPulse® reaches 464 °C, well above the threshold for
               MAPbI /NiO   interaction.  SimPulse®  simulated  temperature  vs.  time  curve  for  PC  25
                     3
                           x
               [Supplementary Figure 7] shows that the temperature at MAPbI /NiO  interface stays above 120 °C for ~154
                                                                          x
                                                                     3
               ms. PC involves non-equilibrium heating, so a direct comparison with TA using hot plates or ovens cannot
               be made. Nonetheless, we believe that these elevated temperatures and extended exposure are sufficient to
               cause the interfacial degradation using PC 25 as the processing condition for MAPbI  on top of NiO . We
                                                                                                     x
                                                                                        3
               postulate that adding a barrier layer capable of withstanding high temperatures could buffer the MAPbI /
                                                                                                         3
               NiO  interfacial reaction. Shutting off the undesired reaction could boost device J-V characteristics back to
                   x
               the level of regular TA counterparts. Previous works have suggested that using a buffer layer can serve as an
               effective barrier to improve performance and perverse the long-term stability of perovskite PSCs made with
               NiO  HTL [26,43] . Another set of PC 25 devices using a NiO  HTL and a PbI  buffer layer were fabricated. As
                                                                              2
                   x
                                                                x
               Figures 4 and 5 show, the PbI  buffer layer did produce a moderate improvement in device PCE, jumping
                                        2
               from 1.19% ± 0.75% to 5.43% ± 0.43%, but still falling far short of the TA MAPbI /NiO  reference. These
                                                                                      3
                                                                                           x
               results give credence to the idea that the issue of decreased J-V characteristics and device PCE is not caused
               by the quality of the PC 25 MAPbI  but more so due to the detrimental interaction of MAPbI  and NiO  at
                                                                                               3
                                                                                                       x
                                             3
               high temperatures.
               Next, we investigated a more recently studied HTL/buffer layer, MeO-2PACz. Depositing MeO-2PACz on
               top of the NiO  HTL and processing MAPbI  using PC 25 produce PSC devices with PCEs slightly better
                            x
                                                      3
               than the TA MAPbI /NiO  reference [Figures 4 and 5, Supplementary Table 5]. Photonic cured PSCs with
                                     x
                                3
               NiO  HTL + MeO-2PACz show a J  of 16.5 mA/cm , closing in on the 17.2 mA/cm  we report for the TA
                                                            2
                                                                                       2
                                             sc
                   x
               MAPbI /NiO  in Supplementary Table 5. The V  and fill factor for the PC 25 sample are boosted slightly
                          x
                                                        oc
                     3
               compared to the TA device. To verify that PC 25 is the optimal PC condition for MAPbI  processing, we
                                                                                            3
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